Three engineering domains, one execution model. Superconducting transmon modules sit at twenty millikelvin. A microwave to optical transducer links them with heralded photons at telecom wavelength. A room temperature decoder farm closes the loop within microseconds. A software runtime hides the partitioning from the application.
Three engineering domains and a software runtime. Each domain has its own clock, its own thermal envelope, and its own engineering programme. They meet only at well-defined contracts: drive lines, syndrome bus, photonic channel, ExecutorContract.
Five chiplets per module, one hundred tantalum on silicon transmons each, heavy hex lattice with one tunable coupler per edge. Chiplet to chiplet routing through superconducting through silicon interconnects, less than 1 dB loss per crossing at six gigahertz.
| Transmons | 500 per module |
| Substrate | Ta on Si |
| Temperature | ≤ 20 mK |
| T₁ coherence | ≥ 200 μs |
Electro optic lithium niobate transducers up convert and down convert microwave photons to telecom band. An SNSPD coincidence click heralds a Bell pair across the channel. Failed attempts do not corrupt the logical state. The transducers are staged at one hundred millikelvin, the detector at 1.5 K.
| Wavelength | 1,550 nm |
| Transduction η | ≥ 0.1% (base) |
| Bell pair F | raw ≥ 0.85 |
| Link latency | ≤ 25 μs |
Two room temperature control racks, one per module, each containing arbitrary waveform generators at one nanosecond resolution, digitisers with synchronised trigger distribution, an FPGA sequencer, and a minimum weight perfect matching decoder substrate. The control loop closes the stabilizer cycle in one microsecond.
| Sample rate | 1 ns |
| Cycle time | 1 μs |
| Syndrome ingest | ≤ 5 μs |
| Feed forward | ≤ 10 μs |
Why three domains, not one box. Each domain runs on its own clock, in its own thermal envelope, on its own engineering programme. The domains meet only at well defined contracts: drive lines and readout buses between compute and control, a phase locked pump tone between control and the photonic transducer, and an ExecutorContract between control and the software runtime. The contracts are what let the modules scale independently of the system clock and the system clock scale independently of the modules.
Five chiplets, one hundred fixed frequency tantalum on silicon transmons each, in the EJ over EC ≈ 50 regime. Heavy hex connectivity, one tunable coupler per edge, matched to a rotated surface code variant.
The transmon is a weakly anharmonic oscillator formed from a Josephson junction shunted by a large capacitance. QONTOS-1 transmons are designed in the EJ/EC ≈ 50 regime, with ω_q / 2π = 5.0 ± 0.2 GHz and α / 2π ≈ −300 MHz.
Fabrication is on high resistivity silicon with tantalum capacitor pads and aluminium Josephson junctions, a stack that has demonstrated T₁ in excess of 300 μs in published device characterisations. The QONTOS-1 device specification targets a process window aware design point: T₁ ≥ 200 μs, T₂_echo ≥ 100 μs, and frequency yield ≥ 90% within a ±20 MHz window after one round of laser trimming.
QONTOS-1 adopts the heavy-hex connectivity demonstrated on IBM Eagle and Condor processors. The heavy-hex graph has vertex degree two or three, sparser than the square-grid topology assumed by the canonical surface code but matched to a rotated-surface-code variant with explicit ancilla qubits. The benefit is a substantial reduction in frequency collision risk: with one tunable coupler per edge, the lattice supports independent calibration of each two qubit gate without the all-to-all frequency matching constraint of fixed-coupler architectures.
Single qubit gates are implemented as resonant microwave drives with derivative removal by adiabatic gate (DRAG) envelopes, applied through Purcell filtered drive lines at the qubit plane. With σ = 4 ns and total pulse length 4σ = 16 ns, the QONTOS-1 target single qubit gate error is 1 × 10⁻⁴ as measured by randomised benchmarking.
Two qubit gates are realised as tunable coupler CZ operations: a transmon coupler placed between every nearest neighbour data qubit pair is biased by a flux pulse to selectively activate the |11⟩→|02⟩ avoided crossing for approximately 18 ns. Net coupling rates are J / 2π ≈ 5 MHz at the activated bias, with idle coupling suppressed below 100 kHz. The QONTOS-1 target CZ error of 5 × 10⁻³ is consistent with published two qubit gate fidelities on similar devices.
Readout is performed via the dispersive shift of a separate linear resonator coupled to each transmon. The qubit state translates into a state dependent phase shift of a probe tone, which is amplified by a Josephson travelling-wave parametric amplifier at the 4 K stage and digitised at room temperature. The QONTOS-1 readout target, F_RO = 99.0% assignment fidelity at 1 μs integration time, is consistent with the noise temperature, dispersive shift, and resonator linewidth selected in the chiplet design.
Each module operates inside a commercial dilution refrigerator. Five thermal stages thermalise the wiring, amplify the readout chain, stage the photonic transducer, and hold the qubit chip at the mixing chamber. Every line in is a thermal load to budget.
Each module operates within a commercial dilution refrigerator with the following stage specification: 50 K and 4 K stages for wiring thermalisation and primary amplification, 100 mK still stage for transducer staging and intermediate filtering, mixing chamber stage at ≤ 20 mK with target cooling power 500 μW at 100 mK and ≥ 25 μW at 20 mK.
Wiring density is constrained to maintain a passive thermal budget below 1 μW at the mixing chamber. Each module is driven by one room temperature control rack housing AWGs with 1 ns sample rate resolution, digitisers with synchronised trigger distribution at sub-ns jitter, and an FPGA sequencer implementing the real time loop. The control rack is connected to the cryogenic stack through a wiring break at the 50 K stage and through Purcell filtered drive lines at the qubit plane.
| Stage | Role | Hardware at this stage | Cooling target |
|---|---|---|---|
| 295 K | Room temperature control plane | AWG · digitiser · FPGA sequencer · decoder farm | W class |
| 50 K | First cooling, wiring break | Attenuators · IR filtering · mechanical wiring break | ~ 1 W |
| 4 K | Second cooling, primary amplification | JTWPA · isolators · multiplexers | ~ 1 mW |
| 100 mK | Still, transducer staging | Photonic transducer · intermediate filtering · optical fibre IO | 500 μW |
| ≤ 20 mK | Mixing chamber, base operating point | 5-chiplet qubit chip · Purcell filters · readout resonators | ≥ 25 μW |
The wiring budget is the bottleneck, not the qubit. Every line that enters the mixing chamber is a thermal load. With ≥ 25 μW of cooling power at 20 mK and a target of less than 1 μW of passive heat from wiring, QONTOS-1 holds the line count and attenuation distribution exactly where the dilution refrigerator can absorb it. Frequency multiplexing of eight readout resonators per amplifier line is what lets the 4 K stage carry the readout fan in without doubling the wire count. The cryogenic envelope is therefore not a constraint imposed on the system; it is the engineering target the device, control, and photonic teams design against.
A microwave photon emitted from a transmon in Module A is parametrically up-converted to 1,550 nm in an electro-optic resonator, sent through low-loss fibre to Module B, and absorbed there. A separate SNSPD click confirms that a photon survived the trip. Only on a herald do the two modules treat the round as a successful Bell pair.
Electro-optic transduction proceeds through three coupled modes: a microwave cavity at ωe near 5 GHz, an optical mode at ωo near 193 THz, and a strong classical pump at ωp = ωo − ωe. The effective microwave-optical coupling rate is geo = g0 · √np, where g0 is the single-photon vacuum coupling and np is the intracavity pump photon number.
In the resolved-sideband regime the transduction efficiency reaches its impedance-matched optimum at cooperativity C = 4geo² / (κe κo) = 1. Engineering the transducer is therefore the engineering of one number.
Module A and Module B both attempt to emit a microwave photon into their local transducer. Up-converted optical photons interfere on a beam splitter sitting on the 1.5 K stage. A single SNSPD click projects the two modules into an entangled Bell state. No click, no entanglement, no harm done: the modules reset and try again. Only the heralded rounds count.
QONTOS-1 is specified to operate in three nested regimes. The base regime is the floor we commit to: it is what the device, fibre, and SNSPD chain are sized for. The aggressive regime is an explicit scenario target. The research threshold is included to show the headroom later fault-tolerant studies would need, not to imply QONTOS-1 commits to it.
| Regime | End-to-end efficiency η | Raw / purified pair rate | What it unlocks |
|---|---|---|---|
| Base | ≥ 0.1 % | 10² to 10⁴ s⁻¹ | Bell-pair physics validation, tomography, link characterisation |
| Aggressive | ≥ 0.5 % | purified-rate dependent | Scenario planning for distributed circuits with explicit purification overhead |
| Research threshold | ≥ 1 % | architecture-study input | FTQC interconnect studies with entanglement purification and noise closure |
For modules separated by 0 to 5 m of optical fibre, end-to-end link latency is dominated by phase-lock acquisition (≈ 10 μs) and decoder ingest (≈ 5 μs). Optical propagation contributes ≤ 25 ns. A dedicated phase-lock subsystem maintains coherence between the pump tones of the two transducers using a shared 10 MHz reference distributed over the same fibre as the Bell-pair photons in a separate wavelength band, with a feedback loop holding sub-100 fs RMS jitter. The 25 μs link latency target is achievable across the full 0 to 5 m range in the base regime.
Heralding makes the link usable, not magic. The photon either arrives, the SNSPD clicks, and the modules commit the Bell pair, or nothing is committed and the runtime simply tries again. QONTOS-1 budgets the retry cost for validation workloads. Logical cross-module operations require purified pairs at much higher effective fidelity, so the compiler treats purified-pair availability as an explicit resource rather than an unlimited primitive.
Quantum error correction only works when every stabilizer cycle, syndrome decode, and feed-forward correction closes inside the qubit coherence window. The QONTOS control loop is specified as a strict hierarchy of nested timescales, each handed off to the tier of hardware that can hold the budget.
Single-qubit gates close in tens of nanoseconds. The stabilizer cycle of the surface code lands inside a microsecond. The decoder must turn each cycle's syndrome into a feed-forward correction within five microseconds. Bell-pair distribution and circuit batching sit two and four decades higher. Calibration sweeps occupy the second band. Every timescale below has to fit inside the timescale above.
The decoder loop has to absorb a sustained five-cycle backlog without losing the qubit. The way QONTOS holds this budget is by partitioning the work across four physical layers: pulse plane (AWG), stabilizer plane (FPGA sequencer), syndrome plane (decoder farm), and runtime plane (room-temperature host). Nothing travels further than it needs to, and nothing blocks on a layer slower than itself.
The decoder latency budget is the spec everything else is sized against. The qubit T₂ has to outlast the decoder by an order of magnitude. The FPGA sample-rate grid has to be coarser than the gate envelope but finer than the stabilizer cycle. The PCIe lane count between the FPGA sequencer and the decoder farm has to absorb the syndrome volume of every active patch. If any one tier in the hierarchy fails to hold its budget, the loop opens and the qubit forgets why it was running.
The QONTOS software platform is the developer-facing interface to the hardware. It is operational today against simulator and external-provider backends, and the same surface becomes the production runtime for QONTOS-1 at first-module bring-up. Three choices shape it: planning is separated from runtime, every backend is addressed through one interface, and every run emits a cryptographic proof chain.
A submitted circuit is normalised, partitioned, scheduled, dispatched, and aggregated. Planning completes entirely before the first hardware tick. The real-time loop executes the prepared plan with no further planning overhead, and the proof chain accumulates a SHA-256 hash at each stage.
Circuits that exceed a single module's qubit envelope are decomposed into partitions, each of which can execute on a single module with cross-module entanglement realised through the photonic interconnect. The compiler picks the partitioner automatically by circuit size, and the user can override it.
Used for circuits below roughly 20 logical qubits. Assigns gates to partitions in topological order. Fast iteration during development.
Default for larger circuits. Constructs the gate-connectivity graph and uses spectral clustering on its Laplacian to minimise the number of inter-partition gates.
Used when the user has supplied an explicit qubit-to-module mapping. Typical for benchmarking or replay-from-proof workloads.
Partitioned execution produces one result per backend. The result aggregator reconstructs the full-circuit distribution from the partition results using the inter-partition gate structure recorded in the partition plan. For product-state partitions the joint distribution is the tensor product of the partition distributions. For entangled partitions, the inter-partition Bell pairs introduce known classical-shadow correlators that are inverted at aggregation.
Every run emits a three-layer cryptographic proof chain. Each layer's hash incorporates the previous layer's hash, so any tampering at any stage invalidates the chain. The proof is a portable artefact that can be replayed by any consumer of the result.
The same software runs against five backends today and against QONTOS-1 at bring-up. Plan-time work is identical regardless of whether the executor is a simulator on a developer's laptop or a future modular machine. That is the point of separating planning from runtime: it is what lets the team validate compiler, partitioner, scheduler, and proof chain against IBM Quantum and Amazon Braket now, and switch the executor over to QONTOS-1 hardware the day the first module accepts a circuit.
A two-qubit logical gate across the photonic interconnect is implemented as a merge-then-split lattice surgery between two surface-code patches. The seam between the patches is not a row of physical transmons. It is a row of Bell pairs delivered by the photonic interconnect, consumed one per code cycle.
Logical qubit A lives on a surface-code patch inside Module A. Logical qubit B lives on a patch inside Module B. To run a logical CNOT, the runtime opens a merged region by measuring a joint X⊗X stabilizer along a strip between the two patches. The strip is populated by Bell pairs heralded across the interconnect. After d code cycles the merge is closed by a split, leaving the two patches in a state equivalent to having executed a transversal CNOT.
A distance-d merge consumes roughly d Bell pairs per code cycle for d code cycles. The total Bell-pair budget therefore scales as d². At the QONTOS-1 base operating regime, the dominant cost of a cross-module logical gate is photonic, not electrical. Raw Bell pairs are sufficient for link validation and tomography; logical operations require purification to much higher effective fidelity, so their timing is governed by the purified-pair supply.
| Operating regime | Pair-rate assumption | Distance-5 merge cost | Cross-module operation interpretation |
|---|---|---|---|
| Base | raw 10² to 10⁴ s⁻¹ | ~ 25 Bell pairs | validation and tomography; not a useful logical-gate claim |
| Aggressive | purified-rate scenario | ~ 25 Bell pairs | multi-logical experiments after purification overhead is budgeted |
| Research | d ≥ 21 supply TBD | ~ 25 Bell pairs | architecture study; decoder and purification fabric not fixed |
At distance d = 5 the merge consumes roughly 25 Bell pairs. With raw fidelity near the QONTOS-1 validation target, those pairs are used to prove the interconnect and measure error channels. A fault-tolerant cross-module gate requires a purified effective pair fidelity near 0.98, so the published timing must include purification overhead instead of assuming raw pairs are directly usable.
Distributed logical operations are why the photonic interconnect exists. Without lattice surgery between modules, every increment in logical-qubit count costs another monolithic chiplet. With it, two modules can share a logical operation through a row of Bell pairs. The conversion rate between those costs is the purified Bell-pair rate, and v5.4 treats that rate as a central open engineering variable rather than an already-retired assumption.