Five tracks · four gates · one weekly review

An engineering programme, not a company campaign.

QONTOS is hosted at the Zhyra Quantum Research Institute. Five engineering tracks run in parallel against four formal gates. Every milestone is a measurable subsystem behaviour, not a calendar event. The whitepaper is the source of truth; this page is the operating record behind it.

Whitepaper v5.4 Contact the programme
PROGRAMME · 5 TRACKS · 4 GATES G1 G2 G3 G4 freeze module Bell pair logical T1 · device T2 · control T3 · interconnect T4 · software T5 · QEC Engineering programme · Abu Dhabi Zhyra Quantum Research Institute · 5 tracks · 4 gates First machine · QONTOS-1 · G1 through G4 two modules · 1,000 qubits · single logical qubit at G4

Five tracks. Four gates. One programme, run with engineering discipline.

PROGRAMME AT A GLANCE

Five numbers, no calendars.

The QONTOS programme commits to subsystem behaviours, not dates. Every number below is anchored to a measurable specification in the whitepaper. Calendar slippage is a metric, not the metric.

ENGINEERING TRACKS

5 device · control · interconnect · software · QEC

FORMAL GATES

4 G1 · G2 · G3 · G4 · public criteria

QONTOS-1 QUBITS

1,000 two modules · 500 transmons each · tantalum-on-silicon

WHITEPAPER PAGES

v5.4 v5.4 · peer-review draft · CC-BY-4.0 source

PROGRAMME TIMELINE

G2 gate first module acceptance · no calendar claim

MISSION · § 0.1

Take quantum computing past the monolithic ceiling.

Monolithic superconducting systems plateau near 1,000 qubits because thermal load, wiring density, frequency crowding, and chiplet yield compound non-linearly inside one envelope. QONTOS resolves the ceiling by separating qubit count from the single-envelope budget. Modules are entangled by heralded microwave-to-optical photonic interconnects. The five-generation arc now separates the QONTOS-1 engineering target, QONTOS-2/3 scenarios, and QONTOS-4/5 research vision.

QONTOS exists to turn a modular architecture from a paper into an operable end-to-end machine at QONTOS-1 scale, and then to extend it across the family arc. The work is engineering, not advocacy. The numbers are public, the gates are public, and the misses are public.

The first machine, QONTOS-1, fields two modules at 500 transmons each, photonically interconnected through a millikelvin transducer, with a one-logical-qubit validation experiment at G4. The successor generations do not scale by calendar promise; they proceed only when the prior gate closes, and QONTOS-4/5 remain research-vision architecture studies.

  1. 01

    Numbers, not narratives.

    Every claim ties to a measurable subsystem behaviour. We publish what works and what does not.

  2. 02

    Open by default.

    Whitepaper, SDK, decoder RTL, datasets, gate criteria. Closed only where IP residency requires.

  3. 03

    Gates over dates.

    Calendars slip. Subsystem behaviours do not lie. The roadmap is keyed to gates G1 through G4.

  4. 04

    One stack, end to end.

    Device, control, interconnect, software, QEC are run by one programme, with one weekly engineering review.

  5. 05

    Provenance on every result.

    Calibration epoch, firmware SHA, compiler version, decoder weights, raw data hash. No silent aggregation.

  6. 06

    External review is a feature.

    Time on the device is reserved for independent labs; their reports are published alongside ours.

FIVE ENGINEERING TRACKS · T1 → T5

Five teams. One device. One weekly engineering review.

The programme is organised around five engineering tracks. Each track owns its subsystem, its specification, and its share of the gate criteria. T4 Software is highlighted because the software platform is the subsystem ready now; the remaining hardware-facing tracks remain programme workstreams.

T1 · DEVICE

Transmons that stay quiet.

Tantalum-on-silicon chiplets, heavy-hex topology, tunable couplers, native-gate set frozen at the chip level. Owns T₁ statistics, calibrated-edge yield, and the chip family roadmap.

Lead
Park J.
Headcount
11 engineers
Output
QC1-DT-500-TaSi · QC1-CC-005-TaSi
Anchor
§ 5.2 · device family

T2 · CONTROL

Pulse-level loops that close in time.

Quantum Machines OPX 1000 deployment, pulse compiler, real-time decoder loop, calibration cadence. Owns the 5.5 µs d=5 decoder budget, the 24-hour epoch, and the calibration record.

Lead
Mehrabi N.
Headcount
9 engineers
Output
OPX firmware · cal pipeline
Anchor
§ 7 · control plane

T3 · INTERCONNECT

Heralded Bell pairs across modules.

Electro-optic transducer, 1,550 nm photonic link, SNSPD detection, heralded Bell-state measurement. Single most novel risk on QONTOS-1. Owns η ≥ 0.1% base acceptance, raw F ≥ 0.85, false-herald fraction, thermal load, and added-noise budgets.

Lead
Khoury A.
Headcount
13 engineers
Output
QC1-IT-1550-V2 transducer
Anchor
§ 6 · photonic interconnect

T4 · SOFTWARE · READY NOW

One SDK, one IR, one proof.

The software platform is already available: open-source qontos-sdk compiler, partitioner, executor contract, simulator integration, and proof artifact. Backend-agnostic today; native QONTOS execution comes with hardware bring-up.

Lead
Ortiz-Suslow D.
Headcount
10 engineers
Output
qontos-sdk · qontos-sim · benchmarks
Anchor
§ 7.4 · runtime

T5 · QEC

Codes, decoders, magic states.

Rotated surface-code roadmap, sparse-blossom decoder reference, magic-state factory cadence, resource estimator. Co-owns the 0.75 percentage-point above-threshold gap and the requirement that ε_L < p_phys is not claimed until QONTOS-2.

Lead
Tamilselvan R.
Headcount
8 researchers
Output
qontos-research · decoder RTL
Anchor
§ 8 · QEC strategy

PROGRAMME GATES · MASTER TIMELINE

Four gates, public criteria.

G1 freezes architecture. G2 lights the first module. G3 lights the interconnect. G4 lights the first logical qubit. Each gate has a published acceptance criterion and a published "what happens on miss" plan.

FIG.G · PROGRAMME GATES · ACCEPTANCE SEQUENCE

G1 prepG1G2 prepG2G3 prepG3G4 prepG4
T1 · DEVICE
chip family freeze 500q module · bring-up module A · live · 2Q err ≤ 5e-3 module B · paired cosmic-ray hardening
T2 · CONTROL
OPX firmware v1 cal pipeline · 24h epoch decoder loop · 5.5 µs cross-module sync drift policy hardening
T3 · INTERCONNECT
thermal budget η ≥ 0.1 % base SNSPD pairing F_Bell ≥ 0.85 · 1 h purification model
T4 · SOFTWARE
qontos-sdk v1 partitioner · 4-factor sched native executor · G2 three-layer proof · public cycle-aware compiler
T5 · QEC
budget v5.4 decoder RTL · open d=5 validation Bell-pair tomography first logical

Each dark bar is the gate-defining work for its track. Lighter bars are concurrent. Crosscutting decisions go through the weekly programme review; track leads are accountable per gate.

Programme charter

An operating record, not a marketing site.

The QONTOS site exists to make the programme operable from the outside in. Whitepaper, gate criteria, steering minutes, missed-gate disclosures, dataset releases, open code, and the role catalogue all live here. None of it is aspirational. If a number is on the page, it is anchored to a measurable subsystem behaviour. If it is not, it is not on the page.

Read the whitepaper. Apply for a role. Submit a research proposal. Run an open dataset against your decoder. Or just track the miss/hit ratio across the five tracks. We publish all of it.

Download whitepaper programme@qontos.xyz